1. Field of the Invention
The present invention involves a structure for controlled pipeline logic, especially a structure which makes the controlled pipeline logic always active and prevents the controlled pipeline logic from exposing its inner functions to avoid being improperly monitored and observed.
2. Description of the Related Art
A sequential logic can be considered as being formed by a combination logic path and memory elements. The combination logic path consists of a plurality of logic gates. The feature of the combination logic path is that, because there is no feedback loop or memory element between the input condition and the output condition, there exists the corresponding between two conditions and the output can be directly represented by a combination of the inputs without regard to the previous state.
Currently, the general clock sequential logic, such as a controller, carries on the systematic management with the technology of state machine. The state machine is a mechanism which will sustain the current condition until the next state is inputted. For example, the clock sequential logic and the state machine are formed by combinational logic elements and memory elements. The memory element may be a flip-flop, which is a binary cell for storing one bit of information. Whenever the logic does not power down, the flip-flop in the state machine will indefinitely sustain its binary condition until the input signal makes it transform into directional state.
The most important characteristic of the clock sequential logic lies in the cost of gates and synthesis effort. These two factors are exponentially related to the complexity of clock sequential logic. Referring to FIG. 1, in the condition that clock sequential logic of clock is very simple, the state machine will make very good result due to the short lead-time of the state machine and the convenience for usage. However, as the requirements of clock sequential logic are more complicated, the state machine tends to lose its superiority in low cost and synthesis effort. In addition, when the logic complexity is over a predetermined level, the cost of a clock sequential logic designed by the state machine will be much higher.
Another way of systematic management is the technology of pipeline. Pipeline is a mechanism that can concurrently process several instructions, each of which is divided into several steps, so as to reduce the average executing time of each instruction and improve the efficiency of CPU. Pipeline divides an instruction into several pipe stages or pipe segments and each pipe stage only executes one part of each instruction. The pipe stages are connected one by one to form a pipeline. The difference between the pipeline and the state machine is that the state of the pipeline changes with the clock, while the state machine will sustain at a certain condition until the next instruction is inputted.
The time from the moment of beginning to execute a pipe stage to the moment when the next pipe stage is going to be done is called a machine cycle. Since all pipe stages need to be executed and finished before forwarding the instruction, the period of the machine cycle is determined by the pipe stage with longest delay. That is to say, the pipeline has the shortcoming of time delay. Furthermore, since the pipeline is in the state of executing instruction all the time, the datum, no matter during the process of pipeline stage or as the final result, can be derived by monitoring in real time. And then the mechanism of the system can be predicted.
Accordingly, the primary object of the present invention is to provide a structure for controlled pipeline logic, which combines advantages of state machine that are convenient to design and easy to use with the pipeline logic that generate great throughput. The controlled pipeline logic is active dynamically thereof so as to avoid improper monitoring and observation.
To achieve the object, the present invention provides a structure of controlled pipeline logic able to deal with many instructions at the same time. The structure comprises a plurality of combinational logic elements responsible for a part of the input. The input and output of each combinational logic element are each connected to a respective flip-flop. A random noise generator regards clock frequency of combinational logic elements and the power consumption as input information to generate random noises so as to emulate the real input. An active condition is set for showing whether the input of the controlled pipeline logic is a real input information or a random noise. So, no matter if the real signal is inputted into the logic or not, and no matter if the logic executes the inner function, controlled pipeline logic keep operating all along. Thus the controlled pipeline logic will not expose its logic functions, as well as avoid improper monitoring and observation.
According to the aforementioned description, the function of the present invention is different from that of the flip-flop in the state machine. The flip-flop serves to determine and execute some specific conditions instead of sustaining in certain conditions. The controlled pipeline logic achieves the advantages of reducing cost and complexity of arrangement and increasing the performance.
The various objects and advantages of the present invention will be more readily understood from the following detailed description with the appended drawing.